E77 VLSI Design: Lab 2
spicey
in partnership with david luong and mark piper
09.19.2005

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abstract.
This lab involves using SPICE and MatLab® to analyze various circuits. Basically, it shows how much easier it is to use SPiCE to perform circuit analysis than modified nodal analysis using MatLab® even though both give yield the same results.

task 1

SPICE ANALYSIS

 


 
* Control section determines type of analysis
.control
destroy all
echo
 
TRAN 0.01m 4m
plot V1 V2 V3
.endc
 
*These next lines give circuit layout (netlist)
R3 V3 0 1k
R2 v2 v3 4k
R1 v1 v2 1k
 
VVin v1 0 SIN(0 4 1k 0 0)
 
.end

MATLAB ANALYSIS

[ click here for the m-file. ]

task 2

SPICE ANALYSIS
 

 


.control
destroy all
echo
 
TRAN 0.001m 2m
plot V1 V2 V3
.endc
 
*These next lines give circuit layout (netlist)
R3 V3 0 1k
R2 v2 v3 1k
C1 v2 v3 1u
R1 v1 v2 1k
 
VVin v1 0 PULSE(0 5 0 0 0 0.0005 .001)
 
.end

MATLAB ANALYSIS

[ click here for the m-file. ]

 

task 3

SPICE ANALYSIS
 
.control
destroy all
echo
 
TRAN 0.001m 2m
plot V1 V2 V3
.endc
 
*These next lines give circuit layout (netlist)
R3 V3 0 1k
R2 v2 v3 4k
R1 v1 v2 1k
 
D1 v2 v3 DMOD
D2 v2 v1 DMOD
 
.MODEL DMOD D Is=1.0e-15 n=1
 
VVin v1 0 SIN(0 4 1k 0 0)
 
.end

MATLAB ANALYSIS

[ click here for the m-file. ]

task 4

SPICE ANALYSIS

.control
destroy all
echo

TRAN 0.001m 2m
plot V1 V2
.endc

*These next lines give circuit layout (netlist)
R3 v2 0 1k

C1 v2 0 1u

D1 v1 v2 DMOD

.MODEL DMOD D Is=1.0e-15 n=1

VVin v1 0 SIN(0 4 1k 0 0)

.end

MATLAB ANALYSIS

[ click here for the m-file. ]