Final Project:
/**** cpu.c *********************************************************/
/*
* Connie Li, Phil Katz, & Katie Stockhammer
* This is our main program. Basically it is an interpreter.
* This cpu takes a file with CISC instructions, converts them to RISC
* instructions, and runs them.
* We implemented our cpu with 8 user-visible registers and a Random Access
* Memory with 32 user-visible locations.
*/
//The Libraries we Included
#include stdio.h>
#include stdlib.h>
#include string.h>
//Global Variables
#define MAXINTSIZE 2147483647
#define MAXCISCSIZE 8
#define CODEMAX 8192
#define LOAD 1
#define STORE 2
#define ADD 3
#define MULT 4
#define NEG 5
#define JUMPNZ 7
#define AND 8
#define OR 9
#define JUMPFLAG 10
#define LOADI 11
#define NOT 12
#define EQUAL 13
#define LST 14
#define WRITELN 15
#define WRITE 16
#define LOADN 17
#define STOREN 18
int registers[8];
int ram[34];
int romctr=0;
int linenum;
FILE * inFilePtr;
FILE * outFilePtr;
struct romLine {
int code, arg1, arg2, cLine;
};
struct romLine rom[CODEMAX];
//Included functions in this file
void initialize();
void interpret();
void compute();
void RISCgen(int code, int arg1, int arg2);
void printRISC(int code, int arg1, int arg2);
/*The main function reads the file of CISC instructions, then
*calls the functions of initialize, interpret, and compute.
*Initialize does just that, it sets initial values for some of
*our registers. Interpret takes the CISC instructions and
*converts them to RISC instructions. Compute takes RISC
*instructions and does the actual computation*/
int main(int argc, char * argv[]) {
if ( argc != 2)
printf( "Incorrect command line arguments\n");
else {
if (( inFilePtr = fopen (argv[1], "r")) != NULL) {
outFilePtr = fopen ("output.txt", "w");
initialize();
interpret();
compute();
}
}
exit(0);
}
/*Initialize sets some registers to their constant values. We
*use these registers for our RISC computations. */
void initialize(){
int i;
for (i=0; i<8; i++){
registers[i]=0;
}
for (i=0; i<32; i++){
ram[i]=0;
}
registers[9]=1;
registers[10]=-1;
//registers 11 and 12 are used for loads and stores
//memory locations 32 and 33 are used for loads and stores
registers[13]=0;
registers[14]=MAXINTSIZE;
}
/*This is our largest function. It reads in CISC instructions from the
*file and then it converts CISC instructions to
*RISC instructions. Since we have many CISC instructions and we had
*to deal with each separate CISC instruction as a separate case, the
*code is quite lengthy. Some CISC instructions convert to a single
*RISC instruction, while others convert to 7 or more RISC instructions.
*When there are two arguments in the comment, the first is the arg1 argument
*and the second is the arg2 argument. For example: ADDRM - register to
*memory means add the value in the arg1 register to the value in the arg2
*memory*/
void interpret() {
int arg1, arg2;
char cisc[MAXCISCSIZE];
char newline;
//FILE * inFilePtr = fopen("test.txt", "r");
fscanf (inFilePtr, "%d%s%d%d%c", &linenum, cisc, &arg1, &arg2, &newline);
while (!feof (inFilePtr)) {
//Case of ADD:
if(!strncmp(cisc, "ADD", 3)) { //ADDITION
switch(cisc[3]) {
case 'R':
switch(cisc[4]) {
case 'M': //ADDRM - register to memory
RISCgen(LOAD, 11, arg2);
RISCgen(ADD, arg1, 11);
break;
case 'R': //ADDRR - register to register
RISCgen(ADD, arg1, arg2);
break;
case 'I': //ADDRI - register to immediate
RISCgen(LOADI, 11, arg2);
RISCgen(ADD, arg1, 11);
break;
case 'N': //ADDRN - register to indirect
RISCgen(LOADN, 11, arg2);
RISCgen(ADD, arg1, 11);
break;
default: //Should never get here
printf("Invalid instruction\n");
exit(0);
break;
}
break;
case 'M':
switch(cisc[4]) {
case 'M': //ADDMM - memory to memory
RISCgen(LOAD, 11, arg1);
RISCgen(LOAD, 12, arg2);
RISCgen(ADD, 11, 12);
RISCgen(STORE, 11, arg1);
break;
case 'R': //ADDMR - memory to register
RISCgen(LOAD, 11, arg1);
RISCgen(ADD, 11, arg2);
RISCgen(STORE, 11, arg1);
break;
case 'I': //ADDMI - memory to immediate
RISCgen(LOAD, 11, arg1);
RISCgen(LOADI, 12, arg2);
RISCgen(ADD, 11, 12);
RISCgen(STORE, 11, arg1);
break;
case 'N': //ADDMN - memory to indirect
RISCgen(LOAD, 11, arg1);
RISCgen(LOADN, 12, arg2);
RISCgen(ADD, 11, 12);
RISCgen(STORE, 11, arg1);
break;
default: //Should never get here
printf("Invalid instruction\n");
exit(0);
break;
}
break;
case 'N':
switch(cisc[4]) {
case 'M': //ADDNM - indirect to memory
RISCgen(LOADN, 11, arg1);
RISCgen(LOAD, 12, arg2);
RISCgen(ADD, 11, 12);
RISCgen(STOREN, 11, arg2);
break;
case 'R': //ADDNR - indirect to register
RISCgen(LOADN, 11, arg1);
RISCgen(ADD, 11, arg2);
RISCgen(STOREN, 11, arg1);
break;
case 'I': //ADDNI - indirect to immediate
RISCgen(LOADN, 11, arg1);
RISCgen(LOADI, 12, arg2);
RISCgen(ADD, 11, 12);
RISCgen(STOREN, 11, arg1);
break;
case 'N': //ADDNN - indirect to indirect
RISCgen(LOADN, 11, arg1);
RISCgen(LOADN, 12, arg2);
RISCgen(ADD, 11, 12);
RISCgen(STOREN, 11, arg1);
break;
default: //should never get here
printf("Invalid instruction\n");
exit(0);
break;
}
break;
default: //should never get here
printf("Invalid instruction\n");
exit(0);
break;
}
}
else
if(!strncmp(cisc, "SUB", 3)) { //SUBTRACT
switch(cisc[3]) {
case 'R':
switch(cisc[4]) {
case 'M': //SUBRM - register to memory
RISCgen(LOAD, 11, arg2);
RISCgen(NEG, 11, 11);
RISCgen(ADD, arg1, 11);
break;
case 'R': //SUBRR - register to register
RISCgen(NEG, arg2, 11);
RISCgen(ADD, arg1, arg2);
break;
case 'I': //SUBRI - register to immediate
RISCgen(LOADI, 11, arg2);
RISCgen(NEG, 11, 11);
RISCgen(ADD, arg1, 11);
break;
case 'N': //SUBRN - register to indirect
RISCgen(LOADN, 11, arg2);
RISCgen(NEG, 11, 11);
RISCgen(ADD, arg1, 11);
break;
default: //should never get here
printf("Invalid instruction\n");
exit(0);
break;
}
break;
case 'M':
switch(cisc[4]) {
case 'M': //SUBMM - memory to memory
RISCgen(LOAD, 11, arg1);
RISCgen(LOAD, 12, arg2);
RISCgen(NEG, 12, 11);
RISCgen(ADD, 11, 12);
RISCgen(STORE, 11, arg1);
break;
case 'R': //SUBMR - memory to register
RISCgen(LOAD, 11, arg1);
RISCgen(NEG, arg2, 11);
RISCgen(ADD, 11, arg2);
RISCgen(STORE, 11, arg1);
break;
case 'I': //SUBMI - memory to immediate
RISCgen(LOAD, 11, arg1);
RISCgen(LOADI, 12, arg2);
RISCgen(NEG, 12, 11);
RISCgen(ADD, 11, 12);
RISCgen(STORE, 11, arg1);
break;
case 'N': //SUBMN - memory to indirect
RISCgen(LOAD, 11, arg1);
RISCgen(LOADN, 12, arg2);
RISCgen(NEG, 12, 11);
RISCgen(ADD, 11, 12);
RISCgen(STORE, 11, arg1);
break;
default: //should never get here
printf("Invalid instruction\n");
exit(0);
break;
}
break;
case 'N':
switch(cisc[4]) {
case 'M': //SUBNM - indirect to memory
RISCgen(LOADN, 11, arg1);
RISCgen(LOAD, 12, arg2);
RISCgen(NEG, 12, 12);
RISCgen(ADD, 11, 12);
RISCgen(STOREN, 11, arg1);
break;
case 'R': //SUBNR - indirect to register
RISCgen(LOADN, 11, arg1);
RISCgen(NEG, arg2, arg2);
RISCgen(ADD, 11, arg2);
RISCgen(STOREN, 11, arg1);
break;
case 'I': //SUBNI - indirect to immediate
RISCgen(LOADN, 11, arg1);
RISCgen(LOADI, 12, arg2);
RISCgen(NEG, 12, 12);
RISCgen(ADD, 11, 12);
RISCgen(STOREN, 11, arg1);
break;
case 'N': //SUBNN - indirect to indirect
RISCgen(LOADN, 11, arg1);
RISCgen(LOADN, 12, arg2);
RISCgen(NEG, 12, 12);
RISCgen(ADD, 11, 12);
RISCgen(STOREN, 11, arg1);
break;
default: //should never get here
printf("Invalid instruction\n");
exit(0);
break;
}
break;
default: //should never get here
printf("Invalid instruction\n");
exit(0);
break;
}
}
else
if(!strncmp(cisc, "MULT", 4)) { //MULT
switch(cisc[4]) {
case 'R':
switch(cisc[5]) {
case 'M': //MULTRM - register to memory
RISCgen(LOAD, 11, arg2);
RISCgen(MULT, arg1, 11);
break;
case 'R': //MULTRR - register to register
RISCgen(MULT, arg1, arg2);
break;
case 'I': //MULTRI - register to immediate
RISCgen(LOADI, 11, arg2);
RISCgen(MULT, arg1, 11);
break;
case 'N': //MULTRN - register to indirect
RISCgen(LOADN, 11, arg2);
RISCgen(MULT, arg1, 11);
break;
default: //Should never get here
printf("Invalid instruction\n");
exit(0);
break;
}
break;
case 'M':
switch(cisc[5]) {
case 'M': //MULTMM - memory to memory
RISCgen(LOAD, 11, arg1);
RISCgen(LOAD, 12, arg2);
RISCgen(MULT, 11, 12);
RISCgen(STORE, 11, arg1);
break;
case 'R': //MULTMR - memory to register
RISCgen(LOAD, 11, arg1);
RISCgen(MULT, 11, arg2);
RISCgen(STORE, 11, arg1);
break;
case 'I': //MULTMI - memory to immediate
RISCgen(LOAD, 11, arg1);
RISCgen(LOADI, 12, arg2);
RISCgen(MULT, 11, 12);
RISCgen(STORE, 11, arg1);
break;
case 'N': //MULTMN - memory to indirect
RISCgen(LOAD, 11, arg1);
RISCgen(LOADN, 12, arg2);
RISCgen(MULT, 11, 12);
RISCgen(STORE, 11, arg1);
break;
default: //should never get here
printf("Invalid instruction\n");
exit(0);
break;
}
break;
case 'N':
switch(cisc[4]) {
case 'M': //MULTNM - indirect to memory
RISCgen(LOADN, 11, arg1);
RISCgen(LOAD, 12, arg2);
RISCgen(MULT, 11, 12);
RISCgen(STOREN, 11, arg1);
break;
case 'R': //MULTNR - indirect to register
RISCgen(LOADN, 11, arg1);
RISCgen(MULT, 11, arg2);
RISCgen(STOREN, 11, arg1);
break;
case 'I': //MULTNI - indirect to immediate
RISCgen(LOADN, 11, arg1);
RISCgen(LOADI, 12, arg2);
RISCgen(MULT, 11, 12);
RISCgen(STOREN, 11, arg1);
break;
case 'N': //MULTNN - indirect to indirect
RISCgen(LOADN, 11, arg1);
RISCgen(LOADN, 12, arg2);
RISCgen(MULT, 11, 12);
RISCgen(STOREN, 11, arg1);
break;
default: //should never get here
printf("Invalid instruction\n");
exit(0);
break;
}
break;
default: //should never get here
printf("Invalid instruction\n");
exit(0);
break;
}
}
else
if(!strncmp(cisc, "INC", 3)) { //INC
switch(cisc[3]) {
case 'R': //INCR - increment the arg1 register
RISCgen(ADD, arg1, 9);
break;
case 'M': //INCM - increment the arg1 memory
RISCgen(LOAD, 11, arg1);
RISCgen(ADD, 11, 9);
RISCgen(STORE, 11, arg1);
break;
default: //should never get here
printf("Invalid instruction\n");
exit(0);
break;
}
}
else
if(!strncmp(cisc, "DEC", 3)) { //DEC
switch(cisc[3]) {
case 'R': //DECR - decrement the arg1 register
RISCgen(ADD, arg1, 10);
break;
case 'M': //DECM - decrement the arg1 memory
RISCgen(LOAD, 11, arg1);
RISCgen(ADD, 11, 10);
RISCgen(STORE, 11, arg1);
break;
default: //should never get here
printf("Invalid instruction\n");
exit(0);
break;
}
}
else
if(!strncmp(cisc, "SWAP", 4)) { //SWAP
switch(cisc[4]) {
case 'R':
switch(cisc[5]){
case 'R': //SWAPRR - register with register
RISCgen(STORE, arg1, 32);
RISCgen(STORE, arg2, 33);
RISCgen(LOAD, arg1, 33);
RISCgen(LOAD, arg2, 32);
break;
case 'M': //SWAPRM - register with memory
RISCgen(STORE, arg1, 32);
RISCgen(LOAD, arg1, arg2);
RISCgen(LOAD, 11, 32);
RISCgen(STORE, 11, arg2);
break;
default: //Should never get here
printf("Invalid instruction\n");
exit(0);
break;
}
break;
case 'M':
switch(cisc[5]){
case 'M': //SWAPMM - memory with memory
RISCgen(LOAD, 11, arg1);
RISCgen(LOAD, 12, arg2);
RISCgen(STORE, 11, arg2);
RISCgen(STORE, 12, arg1);
break;
default: //Should never get here
printf("Invalid instruction\n");
exit(0);
break;
}
break;
default: //Should never get here
printf("Invalid instruction\n");
exit(0);
break;
}
}
else
if(!strncmp(cisc, "AND", 3)) { //AND
switch(cisc[3]) {
case 'R':
switch(cisc[4]){
case 'M': //ANDRM - register with memory
RISCgen(LOAD, 11, arg2);
RISCgen(AND, arg1, 11);
break;
case 'R': //ANDRR - register with register
RISCgen(AND, arg1, arg2);
break;
case 'I': //ANDRI - register with immediate
RISCgen(LOADI, 11, arg2);
RISCgen(AND, arg1, 11);
break;
default: //should never get here
printf("Invalid instruction\n");
exit(0);
break;
}
break;
case 'M':
switch(cisc[4]){
case 'M': //ANDMM - memory with memory
RISCgen(LOAD, 11, arg1);
RISCgen(LOAD, 12, arg2);
RISCgen(AND, 11, 12);
RISCgen(STORE, 11, arg1);
break;
case 'R': //ANDMR - memory with register
RISCgen(LOAD, 11, arg1);
RISCgen(AND, 11, arg2);
RISCgen(STORE, 11, arg1);
break;
case 'I': //ANDMI - memory with immediate
RISCgen(LOAD, 11, arg1);
RISCgen(LOADI, 12, arg2);
RISCgen(AND, 11, 12);
RISCgen(STORE, 11, arg1);
break;
default: //should never get here
printf("Invalid instruction\n");
exit(0);
break;
}
break;
default: //should never get here
printf("Invalid instruction\n");
exit(0);
break;
}
}
else
if(!strncmp(cisc, "OR", 2)) { //OR
switch(cisc[2]) {
case 'R':
switch(cisc[3]){
case 'M': //ORRM - register with memory
RISCgen(LOAD, 11, arg2);
RISCgen(OR, arg1, 11);
break;
case 'R': //ORRR - register with register
RISCgen(OR, arg1, arg2);
break;
case 'I': //ORRI - register with immediate
RISCgen(LOADI, 11, arg2);
RISCgen(OR, arg1, 11);
break;
default: //should never get here
printf("Invalid instruction\n");
exit(0);
break;
}
break;
case 'M':
switch(cisc[3]){
case 'M': //ORMM - memory with memory
RISCgen(LOAD, 11, arg1);
RISCgen(LOAD, 12, arg2);
RISCgen(OR, 11, 12);
RISCgen(STORE, 11, arg1);
break;
case 'R': //ORMR - memory with register
RISCgen(LOAD, 11, arg1);
RISCgen(OR, 11, arg2);
RISCgen(STORE, 11, arg1);
break;
case 'I': //ORRI - register with immediate
RISCgen(LOAD, 11, arg1);
RISCgen(LOADI, 12, arg2);
RISCgen(OR, 11, 12);
RISCgen(STORE, 11, arg1);
default: //SHould never get here
printf("Invalid instruction\n");
exit(0);
break;
}
break;
default: //Should never get here
printf("Invalid instruction\n");
exit(0);
break;
}
}
else
if(!strncmp(cisc, "NOT", 3)) { //NOT
switch(cisc[3]) {
case 'R': //NOTR - not the arg1 register
RISCgen(NOT, arg1, arg1);
break;
case 'M': //NOTM - not the arg1 memory
RISCgen(LOAD, 11, arg1);
RISCgen(NOT, 11, 11);
RISCgen(STORE, 11, arg1);
break;
default: //should never get here
printf("Invalid instruction\n");
exit(0);
break;
}
}
else
if(!strncmp(cisc, "XOR", 3)) { //XOR
switch(cisc[3]) {
case 'R':
switch( cisc[4] ) {
case 'M': //XORRM - register with memory
RISCgen(STORE, arg1, 33);
RISCgen(LOAD, 11, arg2);
RISCgen(OR, arg1, 11);
RISCgen(STORE, arg1, 32);
RISCgen(LOAD, arg1, 33);
RISCgen(AND, arg1, 11);
RISCgen(NOT, arg1, arg1);
RISCgen(LOAD, 12, 32);
RISCgen(AND, arg1, 12);
break;
case 'R': //XORRR - register with register
RISCgen(STORE, arg1, 33);
RISCgen(OR, arg1, arg2);
RISCgen(STORE, arg1, 32);
RISCgen(LOAD, arg1, 33);
RISCgen(AND, arg1, arg2);
RISCgen(NOT, arg1, arg1);
RISCgen(LOAD, 11, 32);
RISCgen(AND, arg1, 11);
break;
case 'I': //XORRI - register with immediate
RISCgen(STORE, arg1, 33);
RISCgen(LOADI, 11, arg2);
RISCgen(OR, arg1, 11);
RISCgen(STORE, arg1, 32);
RISCgen(LOAD, arg1, 33);
RISCgen(AND, arg1, 11);
RISCgen(NOT, arg1, arg1);
RISCgen(LOAD, 12, 32);
RISCgen(AND, arg1, 12);
break;
default: //Should never get here
printf( "Invalid instruction\n" );
exit(0);
break;
}
break;
case 'M':
switch( cisc[4] ) {
case 'M': //XORMM - memory with memory
RISCgen(LOAD, 11, arg1);
RISCgen(LOAD, 12, arg2);
RISCgen(OR, 11, 12);
RISCgen(STORE, 11, 32);
RISCgen(LOAD, 11, arg1);
RISCgen(AND, 11, 12);
RISCgen(NOT, 11, 11);
RISCgen(LOAD, 12, 32);
RISCgen(AND, 11, 12);
RISCgen(STORE, 11, arg1);
break;
case 'R': //XORMR - memory with register
RISCgen(LOAD, 11, arg1);
RISCgen(OR, 11, arg2);
RISCgen(STORE, 11, 32);
RISCgen(LOAD, 11, arg1);
RISCgen(AND, 11, arg2);
RISCgen(NOT, 11, 11);
RISCgen(LOAD, 12, 32);
RISCgen(AND, 11, 12);
RISCgen(STORE, 11, arg1);
break;
case 'I': //XORMI - memory with immediate
RISCgen(LOAD, 11, arg1);
RISCgen(LOADI, 12, arg2);
RISCgen(OR, 11, 12);
RISCgen(STORE, 11, 32);
RISCgen(LOAD, 11, arg1);
RISCgen(AND, 11, 12);
RISCgen(NOT, 11, 11);
RISCgen(LOAD, 12, 32);
RISCgen(AND, 11, 12);
RISCgen(STORE, 11, arg1);
break;
default: //Should never get here
printf( "Invalid instruction\n" );
exit(0);
break;
}
break;
default: //Should never get here
printf("Invalid instruction\n");
exit(0);
break;
}
}
else
if(!strncmp(cisc, "EQ", 2)) { //EQUALS
switch(cisc[2]) {
case 'R':
switch(cisc[3]) {
case 'M': //EQRM - register and memory
RISCgen(LOAD, 11, arg2);
RISCgen(EQUAL, arg1, 11);
break;
case 'R': //EQRR - register and register
RISCgen(EQUAL, arg1, arg2);
break;
case 'I': //EQRI - register and immediate
RISCgen(LOADI, 11, arg2);
RISCgen(EQUAL, arg1, 11);
break;
default: //should never get here
printf( "Invalid instruction\n" );
exit(0);
break;
}
break;
case 'M':
switch( cisc[4] ) {
case 'M': //EQMM - memory and memory
RISCgen(LOAD, 11, arg1);
RISCgen(LOAD, 12, arg2);
RISCgen(EQUAL, 11, 12);
RISCgen(STORE, 11, arg1);
break;
case 'R': //EQMR - memory and register
RISCgen(LOAD, 11, arg1);
RISCgen(EQUAL, 11, arg2);
RISCgen(STORE, 11, arg1);
break;
case 'I': //EQMI - memory and immediate
RISCgen(LOAD, 11, arg1);
RISCgen(LOADI, 12, arg2);
RISCgen(EQUAL, 11, 12);
RISCgen(STORE, 11, arg1);
break;
default: //Should never get here
printf( "Invalid instruction\n" );
exit(0);
break;
}
break;
default: //Should never get here
printf("Invalid instruction\n");
exit(0);
break;
}
}
else
if(!strncmp(cisc, "GRT", 3)) { //GREATER THAN
switch(cisc[3]) {
case 'R':
switch(cisc[4]) {
case 'M': //GRTRM - register and memory
RISCgen(STORE, arg1, 32);
RISCgen(LOAD, 12, arg2);
RISCgen(LST, arg1, 12);
RISCgen(LOAD, 11, 32);
RISCgen(EQUAL, 11, 12);
RISCgen(OR, arg1, 11);
RISCgen(NOT, arg1, arg1);
break;
case 'R': //GRTRR - register and register
RISCgen(STORE, arg1, 32);
RISCgen(LST, arg1, arg2);
RISCgen(LOAD, 11, 32);
RISCgen(EQUAL, 11, arg2);
RISCgen(OR, arg1, 11);
RISCgen(NOT, arg1, arg1);
break;
case 'I': //GRTRI - register and immediate
RISCgen(STORE, arg1, 32);
RISCgen(LOADI, 12, arg2);
RISCgen(LST, arg1, 12);
RISCgen(LOAD, 11, 32);
RISCgen(EQUAL, 11, 12);
RISCgen(OR, arg1, 11);
RISCgen(NOT, arg1, arg1);
break;
}
break;
case 'M':
switch(cisc[4]) {
case 'M': //GRTMM - memory and memory
RISCgen(LOAD, 11, arg1);
RISCgen(LOAD, 12, arg2);
RISCgen(LST, 11, 12);
RISCgen(STORE, 11, 32);
RISCgen(LOAD, 11, arg1);
RISCgen(EQUAL, 11, 12);
RISCgen(LOAD, 12, 32);
RISCgen(OR, 11, 12);
RISCgen(NOT, 11, 11);
RISCgen(STORE, 11, arg1);
break;
case 'R': //GRTMR - memory and register
RISCgen(LOAD, 11, arg1);
RISCgen(LST, 11, arg2);
RISCgen(LOAD, 12, arg1);
RISCgen(EQUAL, 12, arg2);
RISCgen(OR, 11, 12);
RISCgen(NOT, 11, 11);
RISCgen(STORE, 11, arg1);
break;
case 'I': //GRTRI - register and immediate
RISCgen(LOAD, 11, arg1);
RISCgen(LOADI, 12, arg2);
RISCgen(LST, 11, 12);
RISCgen(STORE, 11, 32);
RISCgen(LOAD, 11, arg1);
RISCgen(EQUAL, 11, 12);
RISCgen(LOAD, 12, 32);
RISCgen(OR, 11, 12);
RISCgen(NOT, 11, 11);
RISCgen(STORE, 11, arg1);
break;
default: //should never get here
printf( "Invalid instruction\n" );
exit(0);
break;
}
break;
default: //should never get here
printf("Invalid instruction\n");
exit(0);
break;
}
}
else
if(!strncmp(cisc, "GRE", 3)) { //GREATER THAN OR EQUAL
switch(cisc[3]) {
case 'R':
switch(cisc[4]) {
case 'M': //GRERM - register and memory
RISCgen(LOAD, 11, arg2);
RISCgen(LST, arg1, 11);
RISCgen(NOT, arg1, arg1);
break;
case 'R': //GRERR - register and register
RISCgen(LST, arg1, arg2);
RISCgen(NOT, arg1, arg1);
break;
case 'I': //GRERI - register and immediate
RISCgen(LOADI, 11, arg2);
RISCgen(LST, arg1, 11);
RISCgen(NOT, arg1, arg1);
break;
default: //should never get here
printf( "Invalid instruction\n" );
exit(0);
break;
}
break;
case 'M':
switch(cisc[4]) {
case 'M': //GREMM - memory and memory
RISCgen(LOAD, 11, arg1);
RISCgen(LOAD, 12, arg2);
RISCgen(LST, 11, 12);
RISCgen(NOT, 11, arg1);
RISCgen(STORE, 11, arg1);
break;
case 'R': //GREMR - memory and register
RISCgen(LOAD, 11, arg1);
RISCgen(LST, 11, arg2);
RISCgen(NOT, 11, arg1);
RISCgen(STORE, 11, arg1);
break;
case 'I': //GREMI - memory and immediate
RISCgen(LOAD, 11, arg1);
RISCgen(LOADI, 12, arg2);
RISCgen(LST, 11, 12);
RISCgen(NOT, 11, arg1);
RISCgen(STORE, 11, arg1);
break;
default: //Should never get here
printf( "Invalid instruction\n" );
exit(0);
break;
}
break;
default: //should never get here
printf("Invalid instruction\n");
exit(0);
break;
}
}
else
if(!strncmp(cisc, "LST", 3)) { //LESS THAN
switch(cisc[3]) {
case 'R':
switch(cisc[4]) {
case 'M': //LSTRM - register and memory
RISCgen(LOAD, 11, arg2);
RISCgen(LST, arg1, 11);
break;
case 'R': //LSTRR - register and register
RISCgen(LST, arg1, arg2);
break;
case 'I': //LSTRI - register and immediate
RISCgen(LOADI, 11, arg2);
RISCgen(LST, arg1, 11);
break;
default: //should never get here
printf( "Invalid instruction\n" );
exit(0);
break;
}
break;
case 'M':
switch(cisc[4]) {
case 'M': //LSTMM - memory and memory
RISCgen(LOAD, 11, arg1);
RISCgen(LOAD, 12, arg2);
RISCgen(LST, 11, 12);
RISCgen(STORE, 11, arg1);
break;
case 'R': //LSTMR - memory and register
RISCgen(LOAD, 11, arg1);
RISCgen(LST, 11, arg2);
RISCgen(STORE, 11, arg1);
break;
case 'I': //LSTMI - memory and immediate
RISCgen(LOAD, 11, arg1);
RISCgen(LOADI, 12, arg2);
RISCgen(LST, 11, 12);
RISCgen(STORE, 11, arg1);
break;
default: //should never get here
printf( "Invalid instruction\n" );
exit(0);
break;
}
break;
default: //Should never get here
printf("Invalid instruction\n");
exit(0);
break;
}
}
else
if(!strncmp(cisc, "LSE", 3)) { //LESS THAN OR EQUAL
switch(cisc[3]) {
case 'R':
switch(cisc[4]) {
case 'M': //LSERM - register and memory
RISCgen(STORE, arg1, 32);
RISCgen(LOAD, 12, arg2);
RISCgen(LST, arg1, 12);
RISCgen(LOAD, 11, 32);
RISCgen(EQUAL, 11, 12);
RISCgen(OR, arg1, 11);
break;
case 'R': //LSERR - register and register
RISCgen(STORE, arg1, 32);
RISCgen(LST, arg1, arg2);
RISCgen(LOAD, 11, 32);
RISCgen(EQUAL, 11, arg2);
RISCgen(OR, arg1, 11);
break;
case 'I': //LSERI - register and immediate
RISCgen(STORE, arg1, 32);
RISCgen(LOADI, 12, arg2);
RISCgen(LST, arg1, 12);
RISCgen(LOAD, 11, 32);
RISCgen(EQUAL, 11, 12);
RISCgen(OR, arg1, 11);
break;
default: //should never get here
printf( "Invalid instruction\n" );
exit(0);
break;
}
break;
case 'M':
switch(cisc[4]) {
case 'M': //LSEMM - memory and memory
RISCgen(LOAD, 11, arg1);
RISCgen(LOAD, 12, arg2);
RISCgen(LST, 11, 12);
RISCgen(STORE, 11, 32);
RISCgen(LOAD, 11, arg1);
RISCgen(EQUAL, 11, 12);
RISCgen(LOAD, 12, 32);
RISCgen(OR, 11, 12);
RISCgen(STORE, 11, arg1);
break;
case 'R': //LSEMR - memory and register
RISCgen(LOAD, 11, arg1);
RISCgen(LST, 11, arg2);
RISCgen(LOAD, 12, arg1);
RISCgen(EQUAL, 12, arg2);
RISCgen(OR, 11, 12);
RISCgen(STORE, 11, arg1);
break;
case 'I': //LSERI - register and immediate
RISCgen(LOAD, 11, arg1);
RISCgen(LOADI, 12, arg2);
RISCgen(LST, 11, 12);
RISCgen(STORE, 11, 32);
RISCgen(LOAD, 11, arg1);
RISCgen(EQUAL, 11, 12);
RISCgen(LOAD, 12, 32);
RISCgen(OR, 11, 12);
RISCgen(STORE, 11, arg1);
break;
default: //Should never get here
printf( "Invalid instruction\n" );
exit(0);
break;
}
break;
default: //Should never get here
printf("Invalid instruction\n");
exit(0);
break;
}
}
else
if(!strncmp(cisc, "NEQ", 3)) { //NOT EQUAL
switch(cisc[3]) {
case 'R':
switch(cisc[4]) {
case 'M': //NEQRM - register and memory
RISCgen(LOAD, 11, arg2);
RISCgen(EQUAL, arg1, 11);
RISCgen(NOT, arg1, arg1);
break;
case 'R': //NEQRR - register and register
RISCgen(EQUAL, arg1, arg2);
RISCgen(NOT, arg1, arg1);
break;
case 'I': //NEQRI - register and immediate
RISCgen(LOADI, 11, arg2);
RISCgen(EQUAL, arg1, 11);
RISCgen(NOT, arg1, arg1);
break;
default: //should never get here
printf( "Invalid instruction\n" );
exit(0);
break;
}
break;
case 'M':
switch(cisc[4]) {
case 'M': //NEQMM - memory and memory
RISCgen(LOAD, 11, arg1);
RISCgen(LOAD, 12, arg2);
RISCgen(EQUAL, 11, 12);
RISCgen(NOT, 11, 11);
RISCgen(STORE, 11, arg1);
break;
case 'R': //NEQMR - memory and register
RISCgen(LOAD, 11, arg1);
RISCgen(EQUAL, 11, arg2);
RISCgen(NOT, 11, 11);
RISCgen(STORE, 11, arg1);
break;
case 'I': //NEQMI - memory and immediate
RISCgen(LOAD, 11, arg1);
RISCgen(LOADI, 12, arg2);
RISCgen(EQUAL, 11, 12);
RISCgen(NOT, 11, 11);
RISCgen(STORE, 11, arg1);
break;
default: //should never get here
printf( "Invalid instruction\n" );
exit(0);
break;
}
break;
default: //should never get here
printf("Invalid instruction\n");
exit(0);
break;
}
}
else
if(!strncmp(cisc, "WRITE", 5)) { //WRITE
switch(cisc[5]) {
case 'R':
RISCgen(WRITE, arg1, arg1);
//RISCgen(WRITE, registers[arg1], arg1);
break;
case 'M':
RISCgen(LOAD, 11, arg1);
RISCgen(WRITE, 11, 11);
break;
case 'I':
RISCgen(LOADI, 11, arg1);
RISCgen(WRITE, 11, 11);
//RISCgen(WRITE, arg1, arg1);
break;
case 'L':
RISCgen(WRITELN, 0, 0);
break;
default: //should never get here
printf("Invalid instruction\n");
exit(0);
break;
}
}
else
if(!strncmp(cisc, "JUMP", 4)) { //JUMP
switch(cisc[4]) {
case 'U':
switch(cisc[5]) {
case 'M': //JUMPUM - unconditional memory
RISCgen(LOAD, 11, arg2);
RISCgen(JUMPNZ, 9, 11);
break;
case 'R': //JUMPUR - unconditional register
RISCgen(JUMPNZ, 9, arg2);
break;
case 'I': //JUMPUI - unconditional immediate
RISCgen(LOADI, 11, arg2);
RISCgen(JUMPNZ, 9, 11);
break;
case 'N': //JUMPUN - unconditional indirect
RISCgen(LOADN, 11, arg2);
RISCgen(JUMPNZ, 9, 11);
break;
default: //should never get here
printf( "Invalid instruction\n" );
exit(0);
break;
}
break;
case 'T':
switch(cisc[5]) {
case 'M':
switch(cisc[6]) {
case 'M':
RISCgen(LOAD, 11, arg1);
RISCgen(LOAD, 12, arg2);
RISCgen(JUMPNZ, 11, 12);
break;
case 'R':
RISCgen(LOAD, 11, arg1);
RISCgen(JUMPNZ, 11, arg2);
break;
case'I':
RISCgen(LOAD, 11, arg1);
RISCgen(LOADI, 12, arg2);
RISCgen(JUMPNZ, 11, 12);
break;
case 'N':
RISCgen(LOAD, 11, arg1);
RISCgen(LOADN, 12, arg2);
RISCgen(JUMPNZ, 11, 12);
break;
default:
printf( "Invalid instruction\n" );
exit(0);
break;
}
break;
case 'R':
switch(cisc[6]) {
case 'M':
RISCgen(LOAD, 11, arg2);
RISCgen(JUMPNZ, arg1, 11);
break;
case 'R':
RISCgen(JUMPNZ, arg1, arg2);
break;
case 'I':
RISCgen(LOADI, 11, arg2);
RISCgen(JUMPNZ, arg1, 11);
break;
case 'N':
RISCgen(LOADN, 11, arg2);
RISCgen(JUMPNZ, arg1, 11);
break;
default:
printf( "Invalid instructionasdfasdfa\n" );
exit(0);
break;
}
break;
default:
printf( "Invalid instruction\n" );
exit(0);
break;
}
break;
case 'F':
switch(cisc[5]) {
case 'M':
switch(cisc[6]) {
case 'M':
RISCgen(LOAD, 11, arg1);
RISCgen(LOAD, 12, arg2);
RISCgen(NOT, 11, 11);
RISCgen(JUMPNZ, 11, 12);
break;
case 'R':
RISCgen(LOAD, 11, arg1);
RISCgen(NOT, 11, 11);
RISCgen(JUMPNZ, 11, arg2);
break;
case'I':
RISCgen(LOAD, 11, arg1);
RISCgen(NOT, 11, 11);
RISCgen(LOADI, 12, arg2);
RISCgen(JUMPNZ, 11, 12);
break;
case 'N':
RISCgen(LOAD, 11, arg1);
RISCgen(NOT, 11, 11);
RISCgen(LOADN, 12, arg2);
RISCgen(JUMPNZ, 11, 12);
break;
default:
printf( "Invalid instruction\n" );
exit(0);
break;
}
break;
case 'R':
switch(cisc[6]) {
case 'M':
RISCgen(LOAD, 11, arg2);
RISCgen(NOT, arg1, arg1);
RISCgen(JUMPNZ, arg1, 11);
break;
case 'R':
RISCgen(NOT, arg1, arg1);
RISCgen(JUMPNZ, arg1, arg2);
break;
case 'I':
RISCgen(NOT, arg1, arg1);
RISCgen(LOADI, 11, arg2);
RISCgen(JUMPNZ, arg1, 11);
break;
case 'N':
RISCgen(NOT, arg1, arg1);
RISCgen(LOADN, 11, arg2);
RISCgen(JUMPNZ, arg1, 11);
break;
default:
printf( "Invalid instruction\n" );
break;
}
default:
printf( "Invalid instruction\n" );
exit(0);
break;
}
break;
case 'N':
switch(cisc[5]) {
case 'M':
switch(cisc[6]) {
case 'M':
RISCgen(LOAD, 11, arg1);
RISCgen(LOAD, 12, arg2);
RISCgen(LST, 11, 13);
RISCgen(JUMPNZ, 11, 12);
break;
case 'R':
RISCgen(LOAD, 11, arg1);
RISCgen(LST, 11, 13);
RISCgen(JUMPNZ, 11, arg2);
break;
case 'I':
RISCgen(LOAD, 11, arg1);
RISCgen(LOADI, 12, arg2);
RISCgen(LST, 11, 13);
RISCgen(JUMPNZ, 11, 12);
break;
case 'N':
RISCgen(LOAD, 11, arg1);
RISCgen(LOADN, 12, arg2);
RISCgen(LST, 11, 13);
RISCgen(JUMPNZ, 11, 12);
break;
default:
printf( "Invalid instruction\n" );
exit(0);
break;
}
break;
case 'R':
switch(cisc[6]) {
case 'M':
RISCgen(LOAD, 11, arg2);
RISCgen(LST, arg1, 13);
RISCgen(JUMPNZ, arg1, 11);
break;
case 'R':
RISCgen(LST, arg1, 13);
RISCgen(JUMPNZ, arg1, arg2);
break;
case 'I':
RISCgen(LST, arg1, 13);
RISCgen(LOADI, 11, arg2);
RISCgen(JUMPNZ, arg1, 11);
break;
case 'N':
RISCgen(LST, arg1, 13);
RISCgen(LOADN, 11, arg2);
RISCgen(JUMPNZ, arg1, 11);
break;
default:
printf( "Invalid instruction\n" );
break;
}
break;
default:
printf( "Invalid instruction\n" );
exit(0);
break;
}
break;
default:
printf( "Invalid instruction\n" );
exit(0);
break;
}
}
else
if(!strncmp(cisc, "LOAD", 4)) { //LOAD
switch(cisc[4]) {
case 'R':
RISCgen(LOADI, arg1, arg2);
break;
case 'M':
RISCgen(LOADI, 11, arg2);
RISCgen(STORE, 11, arg1);
break;
default:
printf("Invalid instruction\n");
exit(0);
break;
}
}
fscanf (inFilePtr, "%d%s%d%d%c", &linenum, cisc, &arg1, &arg2, &newline);
}
}
/*The compute function takes the RISC instruction and does the actual
*computations. */
void compute() {
int temp, i=0;
/*romctr--;*/
for (i=0; i< romctr; i++){
// printf( "%d ", i );
int code=rom[i].code;
int arg1=rom[i].arg1;
int arg2=rom[i].arg2;
switch(code) {
case LOAD:
registers[arg1]=ram[arg2];
break;
case LOADI:
registers[arg1]=arg2;
break;
case LOADN:
registers[arg1]=ram[registers[arg2]];
break;
case STORE:
ram[arg2]=registers[arg1];
break;
case STOREN:
ram[registers[arg2]]=registers[arg1];
break;
case ADD:
registers[arg1]= registers[arg1]+registers[arg2];
break;
case MULT:
registers[arg1]= registers[arg1]*registers[arg2];
break;
case NEG:
registers[arg1]= 0 - registers[arg1];
break;
case JUMPNZ:
temp=findCISC(registers[arg2]);
if (temp == -1)
printf( "AAAAAAAHHH\n" );
// fprintf(stdErr, "AAAAHHHHH\n");
if (registers[arg1] != 0)
i = temp-1;
//i= registers[temp];
break;
case AND:
registers[arg1]= registers[arg1] && registers[arg2];
break;
case OR:
registers[arg1]= registers[arg1] || registers[arg2];
break;
case NOT:
registers[arg1]= !registers[arg1];
break;
case EQUAL:
if (registers[arg1] == registers[arg2])
registers[arg1]=1;
//registers[arg1]= MAXINTSIZE;
else
registers[arg1]=0;
break;
case LST:
if (registers[arg1] < registers[arg2])
registers[arg1]=1;
// registers[arg1]= MAXINTSIZE;
else
registers[arg1]=0;
break;
case JUMPFLAG:
// if (flags[arg1] == 1)
i= registers[arg2];
break;
case WRITELN:
printf("\n");
break;
case WRITE: // passed register number that it should write
printf("%d\t", registers[arg1]);
break;
default:
printf("this is not a RISC opcode! YOU, Stockhammer, are a goof!\n");
exit(0);
break;
}
}
}
/*RISCgen puts the RISC instructions into the array of structs*/
void RISCgen(int code, int arg1, int arg2) {
rom[romctr].code=code;
rom[romctr].arg1=arg1;
rom[romctr].arg2=arg2;
rom[romctr].cLine=linenum;
printRISC( code, arg1, arg2 );
romctr++;
// printf("RISC: %d, %d, %d\n", code, arg1, arg2);
}
void printRISC( int code, int arg1, int arg2) {
printf("%d RISC: ", romctr);
switch(code) {
case LOAD:
printf( "LOAD " );
break;
case STORE:
printf( "STORE ");
break;
case ADD:
printf( "ADD ");
break;
case MULT:
printf( "MULT ");
break;
case NEG:
printf( "NEG ");
break;
case JUMPNZ:
printf( "JUMPNZ ");
break;
case AND:
printf( "AND ");
break;
case OR:
printf( "OR ");
break;
case JUMPFLAG:
printf( "JUMPFLAG ");
break;
case LOADI:
printf( "LOADI " );
break;
case NOT:
printf( "NOT " );
break;
case EQUAL:
printf( "EQUAL " );
break;
case LST:
printf( "LST " );
break;
case WRITELN:
printf( "WRITELN " );
break;
case WRITE:
printf( "WRITE " );
break;
case LOADN:
printf( "LOADN " );
break;
case STOREN:
printf( "STOREN " );
break;
default:
printf( "SOMETHING BAD HAPPENED!!!\n" );
exit(0);
break;
}
printf( " %d %d %d\n", arg1, arg2, linenum);
}
/*findCISC takes a CISC line number and finds the first RISC
instruction that was generated by that line*/
int findCISC(int cisc){
int i, rVal=0;
for(i=0; i