In lab three, we basically implemented Von Neumann's IAS Computer, which we refer to as SSC (Simple Swarthmore Computer). We accomplished this task by first creating a state diagram based on the architecture specified in the lab assignment, then translating this machine into VHDL code using Altera software. Our computer implemented an instruction set that allowed data processing, data storage, data movement, and control for both internal RAM and external I/O device (the dips and LED's on a board).
As mentioned before, the architecture of our Simple Swarthmore computer followed that of Von Neumann's IAS Machine. Our computer has two memories; an instruction memory and a main memory. All memory accesses go through the MAR (Memory Address Register) and data gets stored temporarily in the MBR (Memory Buffer Register). The PC (Program Counter) stores the address of the next instruction. We used conditional flags to designate overflow/underflow, swap/carry, read/write. We also allowed for input from the dip switches on a board, and output to the LED digit displays. We transformed the 8 digit binary output into a hex output on the display.
We derived the instruction set directly from the lab instruction page. The SSC has a fixed length instruction set, where each instruction is 10 bits long. However, the opcodes vary in size. The opcodes fall into 4 categories, which can be seen in the following table:
| Group | Opcodes | Opcode Fields | Address/Data field | |
|---|---|---|---|---|
| A | LoadX | 9 down to 8 | 7 downto 0 | |
| B | LoadMX, StoreMX, JumpMX, JumpPlusMX, JumpCarry, JumpOFlow, Add, And, LoadNegMX, SubMX | 9 downto 5 | 4 downto 0 | |
| C | StoreIO, LoadIO | 9 downto 5 | unused 4 downto 0 | |
| D | Inc, Dec, LSH, RSH, Inv, Swap, LoadMMQ, Arithmetic Right Shift, Arithmetic Left Shift | 9 downto 4 | unused 3 downto 0 |
flags(0) <= temp(8); acc <= temp (7 downto 0); --if temp(8) = 1, then we have negative overflow if acc(7) = '0' then if dMBR(7) = '0' then if temp(7) = '1' then flags(0) <= '1'; --if both are positive but result has 1 in high bit, --then we have positive overflow state <= F1 : return to first state
We implemented the memory modules using the lpm_rom and lpm_ram_dq functions provided in VHDL. Both RAM and ROM were designed as unclocked circuits. The ROM represents the instruction memory and is 32 lines of 8 bits each. The RAM is main memory and is 32 lines of 10 bits each. The ROM is loaded from the rom.mif file that we wrote. The ouput of the ROM is a 10 bit variable which is passed to the iMBR and the output of the RAM is an 8 bit variable which is passed to the dMBR.The RAM also has a one bit variable input so that the ssc can either read or write to main memory. Addresses are read from the MAR.
The I/O or general input for the CPU is the set of DIP switches, which is 8 bits. When the switch is pushed down, the input is 0, otherwise it is 1. The ouput of the CPU is a 16 bit variable which is goes directly to the I/O light display. Since the output of the data is 8 bits, we had the output display two hexadecimal digits so that the hexadecimal digit represented by the lower four bits is displayed by the digit on the right and the other is represented by the digit on the left. If the ouput is a negative number, the decimal sign of the left digit is lit. We also used the clock divider from lab 1 to slow down the signal. We had the CPU as the top level of our program and port mapped in the clockdivider.
Submitted as unlinked on the lab submission page.
Submitted as unlinked on the lab submission page.
Please see printouts submitted directly to Dr. Bruce Maxwell.
We wrote an assembler (it is on the unlinked code page).
We implemented a multiplication algorithm in our test programs section
We implemented 4 new instructions: LoadNegMX, SubMX, ArithmeticRightShift(ARSH), ArithmeticLeftShift(ALSH.
LoadNegMX - loads the negative of the contents of the data memory at location x into the acc.
SubMX - Subtracts the contents of memory location x from the accumulator and puts the result back into the acc.
Arithmetic Left/Right shifts - Shift contents of acc, while preserving the sign bit.